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Project: Half Adder with 7-Segment Readout — pcbelectronics.co.uk
PROJECT / BASIC GATES

Half adder with a literal 0/1 readout

This project builds a one-bit half adder from individual 74-series logic gates — an AND gate and an XOR gate, nothing more integrated than that — and reads the result out on two 7-segment displays that simply show "0" or "1". Flip switch A and switch B and watch the Sum and Carry digits respond. It's a small circuit, but it's the same building block that scales up into full binary adders inside a CPU.

Schematic

Schematic of a half adder with 7-segment 0/1 readout An XOR gate computes Sum from inputs A and B, an AND gate computes Carry. Each output passes through an inverter driving four segments of its own 7-segment display to show a literal 0 or 1, while two segments are tied permanently high. +5V SW1 • A A R1 100kΩ +5V SW2 • B B R2 100kΩ XOR ½ 7486 SUM AND ¼ 7408 CARRY ¼ 7404 ¼ 7404 DISP1 sum adef bc 330Ω ×4 ×2 +5V g: n/c DISP2 carry adef bc 330Ω ×4 ×2 +5V g: n/c

Segments b and c are wired straight to +5V because both digits this display ever shows — "0" and "1" — need them lit. Segments a, d, e and f are wired to an inverter, so they light only when the gate's output is 0 (forming a "0"); when the output is 1 they go dark, leaving just b and c lit (forming a "1"). Segment g is never used by either digit, so it's left unconnected.

Parts list

RefPartQty
—74HC86 quad 2-input XOR gate (one gate used)1
—74HC08 quad 2-input AND gate (one gate used)1
—74HC04 hex inverter (two gates used)1
DISP1, DISP2Common-cathode 7-segment display2
—330Ω resistor (six per display: current limiting)12
R1, R2100kΩ resistor (input pull-down)2
SW1, SW2Toggle or slide switch, SPST (A and B inputs)2
—5V supply1

How it works

A half adder answers one question: what's A + B when A and B are single bits? Two things come out of that sum — the result bit itself (Sum) and whether the addition overflowed into a second bit (Carry). Sum is exactly what an XOR gate computes: it's 1 when the inputs differ and 0 when they match, which is precisely how binary addition behaves for a single bit. Carry is exactly what an AND gate computes: it's only 1 when both inputs are 1 — the one case where 1+1 produces a carry into the next column.

Both gate outputs are logic-level signals, not digits, so each one passes through an inverter that drives four segments of its own display. When a gate's output is 0, the inverter's output is 1, lighting segments a, d, e and f — combined with b and c, which are always lit, that traces out a "0". When the gate's output flips to 1, the inverter's output drops to 0, those four segments go dark, and only b and c remain lit — tracing a "1".

Try all four input combinations: 0+0 shows 0 and 0, 0+1 and 1+0 both show 1 and 0, and 1+1 shows 0 on Sum but 1 on Carry — the circuit's way of saying "1+1 = 10 in binary."

Build notes

  • Any 74xx or 74HCxx family part works electrically the same way; 74HC parts are the easiest to find new and run happily from 5V.
  • If you only have 7400 NAND gates on the bench, both gates here can be built from NAND alone, since NAND is a universal gate: AND is a NAND followed by a NAND wired as an inverter, and XOR can be built from four NAND gates — a classic exercise worth trying once you've got this version working.
  • Confirm your displays are common cathode — on a common-anode display this circuit's logic is inverted throughout.
  • Socket the ICs so you can freely swap the AND or XOR gate for a NAND, NOR or OR while experimenting, without re-soldering.
  • This scales: chain a second half adder plus an OR gate on the carries and you've built a full adder, the block that ripples together into a multi-bit binary adder.